Senior DFT Engineer

Senior DFT Engineer - India. Work Location : Bangalore (Old Madras Road) Experience : 6 to 20 years Role Overview : - DFT engineer with strong experience in DFT design and implementation, Synthesis, and Static Timing Analysis. - In this role, you will be responsible for DFT, Synthesis, and Timing analysis of several modules in digital ASICs. What You'll Be Doing : - Implement DFT methodologies and designs including JTAG, Scan, and Memory BIST at module and chip levels. - Work closely with designers to enable designs to be DFT-friendly on modules and sub-systems. - Help identify and fix design issues to enable smooth DFT implementation. - Collaborate with physical implementation engineers and ASIC vendors in implementing DFT features for Automotive grade silicon. - Collaborate with designers to run Synthesis on modules and sub-systems, and identify and fix RTL, timing, and implementation issues. - Work closely with 3rd party IP vendors on proper DFT implementation for the IPs Define test structures, debug structures, and test plans. - Create test vectors, and simulate in various modes. - Verify/Validate DFT requirements are being met in pre-PD and Post-PD stages. - Be a clear communicator with a proven ability to work across functions inside the company, and with partners across the globe. What You'll Have: - Extensive experience in DFT techniques including JTAG, Scan, memory BIST, scan compression, ATPG vector generation, Boundary Scan, and DFT for mixed-signal and digital Ips. - Must have worked with 3rd party mixed-signal IP vendors in implementing DFT. - Experience with timing constraint generation for DFT modes. - Experience with LBIST - Initiation of test sequence on POST tests using IST controllers. - Experience with IEEE JTAG 1149 1/1149 6/1500/1687 and BSDL, ICL, PDL. - Experience with DFT verification and ATE test pattern generation. - Experience with silicon bring-up and debugging on ATE and in-system. - BSEE, MSEE, 7 years experience, or Ph.D. with 2 years of relevant experience in physical implementation of Digital ASICs. Nice To Haves: - Familiarity with developing automotive grade silicon with AEC-Q100 qualification and ISO 26262. (ref:hirist.tech)

Location: Bangalore, IN

Posted Date: 4/24/2024