DFT Engineer - Scan/ATPG

Key Responsibilities : - Implement Scan Insertion and ATPG (Automated Test Pattern Generation) flows for SoC/ASIC designs. - Perform test generation, fault simulation, and coverage analysis to ensure high-quality manufacturing test coverage. - Develop and integrate test patterns for functional and structural testing (e.g., stuck-at fault, transition fault, path delay, etc.). - Collaborate with RTL and physical design teams to ensure proper integration of DFT logic, including scan chains, boundary scan, and BIST (Built-In Self-Test). - Work with the physical design team to ensure that scan insertion and ATPG meet timing and power requirements. - Develop and execute verification plans to ensure complete test coverage, including test vector validation and fault grading. - Optimize ATPG coverage and test time, focusing on compression and fault coverage improvement. - Provide support for silicon bring-up and failure analysis, including diagnosing test coverage gaps and proposing fixes. - Implement Built-In Self-Test (BIST) for both logic and memory elements. Support DFT-related ATE (Automated Test Equipment) activities and ensure that tests are compatible with the test system. - Work closely with cross-functional teams (design, validation, and test) to meet product goals and timelines. - Contribute to improving DFT methodologies and tools to increase efficiency and : - Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. - 4 years of experience in DFT engineering, with a focus on Scan Insertion and ATPG. - Strong knowledge of DFT techniques such as Scan Chains, ATPG, Boundary Scan, BIST, and JTAG. - Experience with DFT tools such as Synopsys DFT Compiler, Mentor Tessent, or Cadence Modus. - Proficiency in System Verilog/Verilog and scripting languages (e.g., TCL, Perl, Python). - Solid understanding of fault models and coverage metrics (e.g., stuck-at, transition fault, path delay fault). - Experience with silicon bring-up, debug, and failure analysis related to test coverage and DFT implementation. - Familiarity with physical design constraints and timing closure in relation to DFT. - Strong problem-solving skills and attention to detail, with the ability to troubleshoot complex test and design issues. - Ability to work collaboratively in a cross-functional team environment. - Good communication skills to clearly report progress, issues, and solutions. (ref:hirist.tech)

Location: bangalore, IN

Posted Date: 4/29/2025